Center of Advanced Studies in Electronics Sciences and Technology (CASEST) organised a 2-day RISC-V workshop under the convenorship of Dr. Bhawna Gomber and Dr. Anjali Priya in collaboration with India Electronics and Semiconductor Association (IESA) as a part of IESA’s Semiconductor Nation-Campus Connect Initiative and VLSI System Design (VSD), Bengaluru. RISC-V is an open standard instruction set architecture relying on known reduced instruction set computer principles. This architecture makes instructions simpler and easier to process. The RISC-V workshop provided participants with an immersive learning experience in the RISC-V instruction set architecture (ISA) and its applications in VLSI chip design. By utilizing the VSDSquadron RISC-V and VLSI Chip Design Educational board, participants were able to get hands-on experience in designing RISC-V-based chips.
Dr. Pradip Thaker, former member executive council, IESA and India Country Head & VP, Engineering: d-Matrix; Mr Sriram Bommakanti, alumnus of CASEST, IESA State Champion and Director of Engineering at Intel Hyderabad; Dr. Kunal Ghosh, Director, VSD; Dr.K.C. James Raju, Dean, School of Physics and Prof. M. Ghanashyam Krishna, Head, CASEST inaugurated the workshop. More than 50 faculty members and students of CASEST and Geethanjali College of Engineering and Technology, Hyderabad enthusiastically participated in the event. Dr Kunal Ghosh and his team provided hands-on tutorials with the VSDSquadron educational board for designing RISC-V-based chips.
This workshop is expected to make the students industry ready in an important area of current technology. CASEST proposes to become an institutional member of IESA which will enable it to have direct interaction with industry partners and gain access to other activities of IESA. The workshop was funded by the Institution of Eminence program of the University.
